User Guide Exclusive: Altiumr To Xpeditionr Translator

Altium Designer → Cadence Xpedition Translator — User Guide

4.1 Visual and connectivity checks

  1. Design integrity: Run Design Rule Check (DRC) and Electrical Rule Check (ERC).
  2. Net connectivity: Compare net counts and critical nets (power, differential pairs).
  3. Component placement: Check reference designators, rotations, and placements.
  4. Layer stackup: Verify layer order, copper thicknesses, dielectric values, and plane connectivity.
  5. Silkscreen and keepouts: Validate silkscreen clipping and keepouts; correct as needed.

4. Post-import verification and fixes

Phase B: Run the Standalone Translator

  1. Launch Altium to Xpedition Translator.
  2. Input Tab:
    • Source File: Browse to MyDesign_Prep.PcbDoc.
    • Netlist File: Browse to MyDesign.NET.
  3. Layer Mapping Tab (Crucial):
    • The translator will show a preview. Map Altium Mechanical 1 → Xpedition BOARD_OUTLINE.
    • Map Altium Keepout → Xpedition PLACE_BOUND.
    • Ignore Altium Drill Drawing layers unless you want non-electrical geometry.
  4. Preferences Tab:
    • Check: "Convert Polygons to Plane Shapes" (Converts Altium hatched pours to Xpedition dynamic planes).
    • Check: "Regenerate Teardrops" (Altium teardrops become Xpedition teardrops via post-process).
    • Uncheck: "Translate 3D Models" (Avoid crash).
  5. Hit Execute. The output will be a folder containing:
    • MyDesign.PCB (Xpedition board file)
    • MyDesign.hkp (Netlist and rules)
    • MyDesign.log (Translation report)

2.2 Required File Generation

From Altium, output:

  • Schematic: ASCII .SchDoc or .PrjSch (unencrypted)
  • PCB: ASCII .PcbDoc
  • Libraries: Integrated .IntLib or exploded .SchLib + .PcbLib
  • Netlist: .NET or .EDIF (as backup)

3.2 Phase 1 – Library Translation (Critical First Step)

Do not translate the design before libraries exist in Xpedition format. altiumr to xpeditionr translator user guide exclusive

  1. Select Altium Library Source – Point to .SchLib / .PcbLib folder.
  2. Mapping Table – Create a CSV mapping for:
    • Altium Footprint → Xpedition Part Number
    • Altium Symbol → Xpedition Gate
  3. Run Library Translation – Output = .lkp (Xpedition Component Library) + .pdb (Part DB).
  4. Validate – Open Xpedition Library Manager. Check for:
    • Pins that flipped orientation (common with multi-gate parts).
    • Missing solder mask swell (Altium’s SolderMaskExpansion often drops).

Step 5: Translate the Design

  • Click Translate to begin the conversion process.
  • The tool will generate a log file to track the translation progress.